As semiconductor devices move to ever smaller dimensions, the space for source/drain contacts is reduced even more than the reduction in scale of the transistor. For example, in the 20 nm generation, the lithographic contact dimension is about 65 nm, and this must be reduced to about 20 nm in the etch. With such drastic reductions, the source/drain contact cannot be guarantee to land on the silicided area of the source/drain. The source/drain contact will frequently impinge on the area between the side of the gate stack and the edge of the silicided area of the source/drain. This critical area must be protected in order to prevent modification of the critical dopant concentration required for advanced junction designs. Further, if a portion of the source/drain contact lands on the gate, the transistor will be shorted. Such source/drain contacts that land on the gate must be prevented from shorting the device or punching through the silicon beneath the gate spacer.